1. Field of the Invention
The present invention relates to an apparatus and method for translating logical addresses for virtual machines. More particularly, it relates to an address translator and address translation process effective for virtual machines of multi-processor type comprising a plurality of virtual processors.
2. Description of the Prior Art
An address translation function is a function for easy and efficient performance of dynamic relocation of a program and a function for efficient translation of a logical address to a real address together with an operating system for supporting a virtual storage. The dynamic relocation is usually performed if capacity of the program to be executed is larger than that of a main storage actually provided. The address translation is performed if an address given by the program is treated as a logical address, The logical address that accesses a storage is translated to a real address for designating a position of a real storage actually provided.
The multi-processor system includes has a plurality of processors which share the same main storage to exchange information under control of a single operating system. In order to make the multi-processor system share the same main storage, it have to has prefix areas that are different from one another in the main storage. The prefix areas are areas that store information specific to the respective processors, including channel status words for I/O control, channel address words, and new and old PSWs for interrupt controls. The multi-processor system has a prefix register provided therein, as shown in FIG. 2, to perform address-translation of the logical address issued from the program to real address and in turn to prefix-translate the real address to an absolute address which is an actual main storage access address. The prefix translation includes the following three types.
(1) For the real address access to page 0, the address indicted by contents of the prefix register is the absolute address. PA1 (2) If the real address is the same as the contents of the prefix register and the real address, the address accessing to page 0 is the absolute address. PA1 (3) If the real address does not access to page 0 and is not the same as the contents of the prefix register, the real address is the absolute address.
In a multi-processor system having two processors, as an example, a processor 0 has a prefix register value of "0" and a processor 1 has a prefix register value of ".alpha.," as shown in FIG. 3. The processor 0 translates real address 0 to absolute address 0 and real address .alpha. to absolute address .alpha., and the processor 1 translates real address 0 to absolute address .alpha. and real address .alpha. to absolute address 0.
In general, a translation lookaside buffer (TLB) has the absolute addresses put therein to correspond to the logical addresses to perform faster address translation. As the multi-processor system has one TLB in each processor, the TLB has a result of the prefix translation put therein which is made with use of the prefix register of the respective processor.
The virtual computer system used herein is a control system for performing control as if a plurality of computers (machines) exist and are controlled by a single real machine, which includes processors, a real storage, a channel, and I/O units. In the virtual machine system, of course, the main storage and I/O units are arranged so that a number of operating systems can be run in the single real machine at the same time to share all the resources such as the processors. For the multi-processor system of a virtual machine, the whole multi-processor system in the real machine corresponds to the virtual machines, and the processors of the real machine correspond to virtual processors of the virtual machine. The multi-processor system of virtual machines has to have a TLB entry for each of the virtual processors as each processor of the real machine has only one TLB.
A conventional system of the type described, for example, in the IBM System/370, Extended Architecture, Interpretive Execution. SA22-7095-1, p2 and pp18-19, is intended for providing a multi-processor system in which guests (virtual machines) can share the main storage. Each of the guest CPUs (virtual processors) is defined by an independent state description. Guest type TLB entries are made different depending on the environmental information of the guests. The environmental information of the guests includes the state description. That is, the virtual machine is made as a multi-processor system comprising a plurality of virtual processors, and each virtual processor has a different TLB entry. It is possible to identify all areas, including the prefix areas corresponding to the virtual processors.
If the conventional system described above should be made as the multi-processor system in which any of the virtual machine comprises a plurality of virtual processors, the prefix area of each virtual processor is identified so that the TLB entries for all of the areas, including the prefix areas, are made different specifically for the virtual processors. This eventually results in that a different TLB entry for any of the areas (common among the virtual processors) other than the prefix areas is put in the TLB for each of the specific virtual processors irrespective of the fact that the information other than the ones identifying the virtual processors are identical. In addition, the TLB is occupied by the TLB entry for the area common among the virtual processors as the TLB entry for the prefix area needs a single entry for each virtual processor. As a result, the TLB is excessively occupied by the redundant TLB entry. This decreases efficiency of the TLB, which lowers performance of the virtual machine.